How To Read Register Values Arm
ARM uses a load-store model for memory access which means that only load/store (LDR and STR) instructions can admission memory. While on x86 near instructions are allowed to directly operate on data in memory, on ARM information must be moved from retention into registers before being operated on. This means that incrementing a 32-fleck value at a particular retentivity address on ARM would require three types of instructions (load, increment, and store) to showtime load the value at a item address into a register, increment information technology within the register, and shop it back to the memory from the annals.
To explicate the fundamentals of Load and Store operations on ARM, we beginning with a basic example and continue with three bones commencement forms with three different address modes for each offset form. For each example we will utilise the same piece of assembly code with a different LDR/STR showtime grade, to keep information technology uncomplicated. The best mode to follow this part of the tutorial is to run the code examples in a debugger (GDB) on your lab surround.
- Offset form: Immediate value as the offset
- Addressing mode: Offset
- Addressing way: Pre-indexed
- Addressing mode: Post-indexed
- Offset grade: Register as the offset
- Addressing manner: First
- Addressing mode: Pre-indexed
- Addressing mode: Post-indexed
- Beginning form: Scaled register as the showtime
- Addressing mode: Offset
- Addressing mode: Pre-indexed
- Addressing mode: Post-indexed
Starting time basic example
Generally, LDR is used to load something from retentiveness into a register, and STR is used to store something from a register to a retention address.
LDR R2, [R0] @ [R0] - origin address is the value establish in R0. STR R2, [R1] @ [R1] - destination accost is the value institute in R1.
LDR operation: loads thevalue at the address found in R0 to the destination annals R2.
STR functioning: stores the value found in R2 to the memory address institute in R1.
This is how it would look like in a functional assembly program:
.data /* the .data department is dynamically created and its addresses cannot exist hands predicted */ var1: .word 3 /* variable 1 in memory */ var2: .word iv /* variable 2 in retentivity */ .text /* start of the text (code) section */ .global _start _start: ldr r0, adr_var1 @ load the memory address of var1 via label adr_var1 into R0 ldr r1, adr_var2 @ load the memory address of var2 via label adr_var2 into R1 ldr r2, [r0] @ load the value (0x03) at memory address establish in R0 to register R2 str r2, [r1] @ store the value found in R2 (0x03) to the memory address constitute in R1 bkpt adr_var1: .give-and-take var1 /* address to var1 stored here */ adr_var2: .word var2 /* address to var2 stored hither */
At the bottom we accept our Literal Pool (a retentivity area in the same code section to store constants, strings, or offsets that others tin can reference in a position-contained manner) where nosotros store the retentivity addresses of var1 and var2 (defined in the information section at the top) using the labels adr_var1 and adr_var2. The first LDR loads the address of var1 into register R0. The 2d LDR does the aforementioned for var2 and loads it to R1. Then we load the value stored at the retention address establish in R0 to R2, and shop the value found in R2 to the memory address found in R1.
When we load something into a register, the brackets ([ ]) mean: the value institute in the register between these brackets is a retentiveness address nosotros want to load something from.
When we store something to a retention location, the brackets ([ ]) hateful: the value found in the register between these brackets is a memory address we desire to store something to.
This sounds more complicated than it actually is, so here is a visual representation of what's going on with the memory and the registers when executing the lawmaking above in a debugger:
Let'due south look at the same lawmaking in a debugger.
gef> disassemble _start Dump of assembler lawmaking for role _start: 0x00008074 <+0>: ldr r0, [pc, #12] ; 0x8088 <adr_var1> 0x00008078 <+4>: ldr r1, [pc, #12] ; 0x808c <adr_var2> 0x0000807c <+8>: ldr r2, [r0] 0x00008080 <+12>: str r2, [r1] 0x00008084 <+sixteen>: bx lr Finish of assembler dump.
The labels we specified with the first two LDR operations inverse to [pc, #12]. This is chosen PC-relative addressing. Because we used labels, the compiler calculated the location of our values specified in the Literal Pool (PC+12). You can either summate the location yourself using this exact arroyo, or y'all tin employ labels like we did previously. The only divergence is that instead of using labels, you need to count the exact position of your value in the Literal Pool. In this instance, it is 3 hops (iv+iv+4=12) away from the effective PC position. More about PC-relative addressing after in this chapter.
Side notation: In case yous forgot why the effective PC is located two instructions ahead of the current one, it is described in Function 2 [… During execution, PC stores the accost of the current instruction plus viii (two ARM instructions) in ARM state, and the current teaching plus 4 (two Pollex instructions) in Thumb state. This is different from x86 where PC always points to the next instruction to be executed…].
1.Commencement form: Immediate value as the offset
STR Ra, [Rb, imm] LDR Ra, [Rc, imm]
Here we utilize an immediate (integer) every bit an offset. This value is added or subtracted from the base annals (R1 in the case below) to access information at an offset known at compile time.
.data var1: .word 3 var2: .word 4 .text .global _start _start: ldr r0, adr_var1 @ load the retentiveness address of var1 via label adr_var1 into R0 ldr r1, adr_var2 @ load the memory accost of var2 via label adr_var2 into R1 ldr r2, [r0] @ load the value (0x03) at retention address found in R0 to register R2 str r2, [r1, #2] @ address mode: offset. Shop the value found in R2 (0x03) to the memory address institute in R1 plus two. Base register (R1) unmodified. str r2, [r1, #four]! @ address style: pre-indexed. Store the value found in R2 (0x03) to the retention accost plant in R1 plus 4. Base of operations register (R1) modified: R1 = R1+4 ldr r3, [r1] , #iv @ accost mode: post-indexed. Load the value at retentiveness address constitute in R1 to register R3. Base register (R1) modified: R1 = R1+4 bkpt adr_var1: .give-and-take var1 adr_var2: .word var2
Let'due south phone call this programme ldr.s, compile it and run information technology in GDB to run into what happens.
$ as ldr.s -o ldr.o $ ld ldr.o -o ldr $ gdb ldr
In GDB (with gef) we set a pause point at _start and run the programme.
gef> break _start gef> run ... gef> nexti three /* to run the next 3 instructions */
The registers on my organization are now filled with the post-obit values (go along in mind that these addresses might be different on your organization):
$r0 : 0x00010098 -> 0x00000003 $r1 : 0x0001009c -> 0x00000004 $r2 : 0x00000003 $r3 : 0x00000000 $r4 : 0x00000000 $r5 : 0x00000000 $r6 : 0x00000000 $r7 : 0x00000000 $r8 : 0x00000000 $r9 : 0x00000000 $r10 : 0x00000000 $r11 : 0x00000000 $r12 : 0x00000000 $sp : 0xbefff7e0 -> 0x00000001 $lr : 0x00000000 $pc : 0x00010080 -> <_start+12> str r2, [r1] $cpsr : 0x00000010
The side by side instruction that will be executed a STR operation with the offset address manner . It volition store the value from R2 (0x00000003) to the memory address specified in R1 (0x0001009c) + the outset (#ii) = 0x1009e.
gef> nexti gef> ten/west 0x1009e 0x1009e <var2+2>: 0x3
The side by side STR operation uses the pre-indexed address fashion . Yous can recognize this fashion by the exclamation marker (!). The merely deviation is that the base annals will be updated with the final memory accost in which the value of R2 will be stored. This means, nosotros store the value found in R2 (0x3) to the retentivity address specified in R1 (0x1009c) + the offset (#4) = 0x100A0, and update R1 with this exact address.
gef> nexti gef> 10/w 0x100A0 0x100a0: 0x3 global environment facility> info register r1 r1 0x100a0 65696
The last LDR operation uses the post-indexed accost mode . This means that the base register (R1) is used as the last address, then updated with the offset calculated with R1+4. In other words, information technology takes the value found in R1 (not R1+4), which is 0x100A0 and loads it into R3, and so updates R1 to R1 (0x100A0) + offset (#4) = 0x100a4.
gef> info annals r1 r1 0x100a4 65700 gef> info annals r3 r3 0x3 3
Here is an abstruse illustration of what'south happening:
two.Offset grade: Register as the offset.
STR Ra, [Rb, Rc] LDR Ra, [Rb, Rc]
This commencement class uses a annals equally an offset. An example usage of this showtime form is when your code wants to access an array where the index is computed at run-fourth dimension.
.data var1: .word 3 var2: .give-and-take four .text .global _start _start: ldr r0, adr_var1 @ load the retention address of var1 via label adr_var1 to R0 ldr r1, adr_var2 @ load the memory address of var2 via label adr_var2 to R1 ldr r2, [r0] @ load the value (0x03) at memory address found in R0 to R2 str r2, [r1, r2] @ address mode: showtime. Store the value establish in R2 (0x03) to the retention address constitute in R1 with the commencement R2 (0x03). Base register unmodified. str r2, [r1, r2]! @ accost mode: pre-indexed. Store value found in R2 (0x03) to the memory address plant in R1 with the offset R2 (0x03). Base register modified: R1 = R1+R2. ldr r3, [r1], r2 @ address mode: post-indexed. Load value at retentivity address found in R1 to annals R3. And then modify base of operations register: R1 = R1+R2. bx lr adr_var1: .word var1 adr_var2: .word var2
Subsequently executing the commencement STR operation with the kickoff address mode , the value of R2 (0x00000003) volition be stored at memory accost 0x0001009c + 0x00000003 = 0x0001009F.
gef> x/w 0x0001009F 0x1009f <var2+three>: 0x00000003 The second STR operation with the pre-indexed accost mode will do the same, with the difference that it will update the base register (R1) with the calculated retention address (R1+R2).
gef> info annals r1 r10x1009f 65695 The terminal LDR functioning uses the post-indexed address mode and loads the value at the memory address found in R1 into the register R2, and then updates the base of operations register R1 (R1+R2 = 0x1009f + 0x3 = 0x100a2).
gef> info annals r1 r1 0x100a2 65698 gef> info register r3 r30x3 three
3.Offset course: Scaled annals equally the offset
LDR Ra, [Rb, Rc, <shifter>] STR Ra, [Rb, Rc, <shifter>]
The third offset class has a scaled register as the commencement. In this case, Rb is the base of operations register and Rc is an immediate beginning (or a annals containing an immediate value) left/right shifted (<shifter>) to calibration the immediate. This means that the barrel shifter is used to calibration the commencement. An instance usage of this commencement form would exist for loops to iterate over an array. Here is a uncomplicated example you tin can run in GDB:
.data var1: .word three var2: .word 4 .text .global _start _start: ldr r0, adr_var1 @ load the memory address of var1 via characterization adr_var1 to R0 ldr r1, adr_var2 @ load the retentiveness accost of var2 via label adr_var2 to R1 ldr r2, [r0] @ load the value (0x03) at memory address found in R0 to R2 str r2, [r1, r2, LSL#2] @ address mode: get-go. Store the value institute in R2 (0x03) to the memory address constitute in R1 with the offset R2 left-shifted by 2. Base annals (R1) unmodified. str r2, [r1, r2, LSL#2]! @ accost fashion: pre-indexed. Shop the value found in R2 (0x03) to the memory address found in R1 with the offset R2 left-shifted by two. Base register modified: R1 = R1 + R2<<2 ldr r3, [r1], r2, LSL#2 @ address style: post-indexed. Load value at memory accost found in R1 to the annals R3. And so modifiy base register: R1 = R1 + R2<<two bkpt adr_var1: .word var1 adr_var2: .word var2
The offset STR operation uses the offset address way and stores the value constitute in R2 at the memory location calculated from [r1, r2, LSL#2], which means that it takes the value in R1 as a base (in this example, R1 contains the retentiveness address of var2), then it takes the value in R2 (0x3), and shifts information technology left past two. The picture below is an attempt to visualize how the retentivity location is calculated with [r1, r2, LSL#2].
The second STR operation uses the pre-indexed accost mode . This means, information technology performs the same activeness as the previous operation, with the difference that it updates the base register R1 with the calculated memory accost subsequently. In other words, information technology will start store the value found at the memory address R1 (0x1009c) + the outset left shifted by #2 (0x03 LSL#two = 0xC) = 0x100a8, and update R1 with 0x100a8.
gef> info annals r1 r1 0x100a8 65704 The last LDR functioning uses the post-indexed address mode . This means, it loads the value at the retentiveness address constitute in R1 (0x100a8) into register R3, then updates the base register R1 with the value calculated with r2, LSL#2. In other words, R1 gets updated with the value R1 (0x100a8) + the offset R2 (0x3) left shifted by #2 (0xC) = 0x100b4.
gef> info annals r1 r10x100b4 65716 Summary
Recollect the 3 offset modes in LDR/STR:
- offset way uses an immediate every bit start
- ldr r3, [r1, #4]
- beginning style uses a annals equally offset
- ldr r3, [r1, r2]
- start mode uses a scaled register every bit start
- ldr r3, [r1, r2, LSL#2]
How to call up the different address modes in LDR/STR:
- If there is a !, information technology's prefix accost mode
- ldr r3, [r1, #four]!
- ldr r3, [r1, r2]!
- ldr r3, [r1, r2, LSL#2]!
- If the base register is in brackets past itself, it's postfix address style
- ldr r3, [r1], #four
- ldr r3, [r1], r2
- ldr r3, [r1], r2, LSL#2
- Anything else is offset accost mode.
- ldr r3, [r1, #4]
- ldr r3, [r1, r2]
- ldr r3, [r1, r2, LSL#two]
LDR is not but used to load data from retentivity into a annals. Sometimes you will see syntax like this:
.department .text .global _start _start: ldr r0, =jump /* load the address of the function label jump into R0 */ ldr r1, =0x68DB00AD /* load the value 0x68DB00AD into R1 */ jump: ldr r2, =511 /* load the value 511 into R2 */ bkpt
These instructions are technically called pseudo-instructions. We can employ this syntax to reference data in the literal pool. The literal pool is a retention area in the same section (because the literal pool is part of the lawmaking) to store constants, strings, or offsets. In the example higher up we use these pseudo-instructions to reference an offset to a office, and to move a 32-bit constant into a annals in one instruction. The reason why we sometimes need to use this syntax to motility a 32-bit constant into a register in one educational activity is because ARM can only load a 8-flake value in 1 go. What? To sympathise why, you need to know how immediate values are being handled on ARM.
Loading immediate values in a register on ARM is non as straightforward as it is on x86. In that location are restrictions on which immediate values you can use. What these restrictions are and how to deal with them isn't the most exciting part of ARM assembly, but acquit with me, this is just for your agreement and there are tricks you lot can use to bypass these restrictions (hint: LDR).
We know that each ARM instruction is 32bit long, and all instructions are conditional. There are sixteen condition codes which we can use and 1 status code takes up 4 $.25 of the instruction. Then we need 2 bits for the destination register. two bits for the first operand register, and one bit for the gear up-status flag, plus an contrasted number of bits for other matters similar the actual opcodes. The betoken hither is, that after assigning bits to educational activity-blazon, registers, and other fields, there are only 12 bits left for immediate values, which will simply allow for 4096 unlike values.
This means that the ARM pedagogy is only able to utilize a limited range of firsthand values with MOV directly. If a number can't be used directly, information technology must be carve up into parts and pieced together from multiple smaller numbers.
Merely in that location is more. Instead of taking the 12 $.25 for a single integer, those 12 bits are separate into an 8bit number (n) being able to load whatever 8-bit value in the range of 0-255, and a 4bit rotation field (r) being a right rotate in steps of two between 0 and 30. This means that the full immediate value v is given past the formula: v = n ror two*r. In other words, the only valid immediate values are rotated bytes (values that can exist reduced to a byte rotated by an even number).
Hither are some examples of valid and invalid immediate values:
Valid values: #256 // 1 ror 24 --> 256 #384 // 6 ror 26 --> 384 #484 // 121 ror thirty --> 484 #16384 // 1 ror xviii --> 16384 #2030043136 // 121 ror 8 --> 2030043136 #0x06000000 // six ror 8 --> 100663296 (0x06000000 in hex) Invalid values: #370 // 185 ror 31 --> 31 is not in range (0 – 30) #511 // 1 1111 111one --> bit-pattern tin't fit into one byte #0x06010000 // i 1000 000i.. --> fleck-pattern can't fit into 1 byte
This has the consequence that it is not possible to load a total 32bit address in ane go. We can bypass this restrictions by using one of the post-obit two options:
- Construct a larger value out of smaller parts
- Instead of using MOV r0, #511
- Carve up 511 into two parts: MOV r0, #256, and ADD r0, #255
- Use a load construct 'ldr r1,=value' which the assembler volition happily catechumen into a MOV, or a PC-relative load if that is not possible.
- LDR r1, =511
If you try to load an invalid immediate value the assembler will mutter and output an error saying: Error: invalid constant. If you lot encounter this error, yous now know what it means and what to do about it.
Let's say you desire to load #511 into R0.
.section .text .global _start _start: mov r0, #511 bkpt
If y'all try to get together this lawmaking, the assembler will throw an error:
azeria@labs:~$ every bit test.s -o test.o test.south: Assembler messages: exam.due south:5: Error: invalid constant (1ff) subsequently fixup
You need to either split 511 in multiple parts or yous use LDR as I described earlier.
.section .text .global _start _start: mov r0, #256 /* 1 ror 24 = 256, then it's valid */ add together r0, #255 /* 255 ror 0 = 255, valid. r0 = 256 + 255 = 511 */ ldr r1, =511 /* load 511 from the literal pool using LDR */ bkpt
If you need to figure out if a certain number can be used as a valid firsthand value, you don't need to calculate it yourself. You tin can use my little python script chosen rotator.py which takes your number as an input and tells you if information technology can exist used every bit a valid immediate number.
azeria@labs:~$ python rotator.py Enter the value you want to check: 511 Sorry, 511 cannot be used as an immediate number and has to be split. azeria@labs:~$ python rotator.py Enter the value you want to check: 256 The number 256 tin can be used as a valid immediate number. 1 ror 24 --> 256
How To Read Register Values Arm,
Source: https://azeria-labs.com/memory-instructions-load-and-store-part-4/
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